Cypress Semiconductor /psoc63 /CSD0 /SENSE_PERIOD

The length-1 of the Sense modulation ‘clock’ period in clk_csd cycles. For regular CSD one sense clock cycle = one conversion (=phi1+phi2) . Note this is the base divider, clock dithering may change the actual period length. Note that SENSE_DIV must be at least 1 and additionally also allow for one clk_hf of non overlap (if OVERLAP_HI1/2 is set) on both phases, i.e. if clk_csd=clk_hf then SENSE_DIV must be >=3. In addition the FILTER_DELAY needs to be added to the minimum allowed SENSE_DIV value.

Selects the length of the LFSR which determines the LFSR repeat period. LFSR_BITS LSB of the LFSR are used for the clock dithering variation on the base period (was PRS in CSDv1). Whenever the LFSR is used (non zero value in this field) the LFSR_CLEAR bit should also be set.

0 (OFF): Don’t use clock dithering (=spreadspectrum) (LFSR output value is zero)

1 (6B): 6-bit LFSR (G(x)=X^6 +X^4+X^3+ X+1, period= 63)

2 (7B): 7-bit LFSR (G(x)=X^7 +X^4+X^3+X^2+1, period= 127)

3 (9B): 9-bit LFSR (G(x)=X^9 +X^4+X^3+ X+1, period= 511)

4 (10B): 10-bit LFSR (G(x)=X^10+X^4+X^3+ X+1, period= 1023)

5 (8B): 8-bit LFSR (G(x)=X^8+X^4+X^3+X^2+1, period= 255)

6 (12B): 12-bit LFSR (G(x)=X^12+X^7+X^4+X^3+1, period= 4095)

Shift the LFSR output left by LSFR_SCALE bits before adding to SENSE_DIV. This dithering is disabled when SEL_LSFR_MSB is set. The clock divider to be used = (SENSE_DIV+1) + (SEL_LSFR_MSB ? 0 : (LFSR_OUT<<LFSR_SCALE)). Note that the clock divider including the dithering term must fit in 12 bits, otherwise the result is undefined.

When set, forces the LFSR to it’s initial state (all ones). This bit is automatically cleared by hardware after the LFSR is cleared, which is at the next clk_csd positive edge. This bit should be set whenever this register is written and the LFSR is used. Note that the LFSR will also get reset to all ones during the AutoZero_1/2 states.

Use the MSB of configured LSFR size as csd_sense signal. Intended to be used only with bit 8 or 12-bit LFSR size for CSDv1 backward compatibility (PRS). When this bit is set then clock divider dithering is disabled and SENSE_WIDTH is disabled.

Selects the number of LSB bits to use from the LSFR to provide the clock dithering variation on the base period. Caveat make sure that SENSE_DIV > the maximum absolute range (e.g. for 4B SENSE_DIV > 8), otherwise results are undefined.

0 (2B): use 2 bits: range = [-2,1]

1 (3B): use 3 bits: range = [-4,3]

2 (4B): use 4 bits: range = [-8,7]

3 (5B): use 5 bits: range = [-16,15] (default)